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DS1680 Portable System Controller with Touch-Screen Control
www.maxim-ic.com
FEATURES
Real-time clock (RTC) - Counts seconds, minutes, hours, date, month, day of the week, and year with leap-year compensation valid up to 2100 - Power control circuitry supports system power-on from day/time alarm Microprocessor monitor - Halts microprocessor during power- fail - Automatically restarts microprocessor after power failure - Monitors pushbutton for external override - Halts and resets an out of control microprocessor NV RAM control - Automatic battery backup and write protection to external SRAM 1.25V threshold detector for power- fail warning 10-bit analog-to-digital converter (ADC) - Monotonic with no missing codes Four-wire analog resistive touch-screen interface
PIN ASSIGNMENT
I/O SCLK CEO PFO V CCO CS V CC RST CEI 34 33 PFI GND D7 D6 D5 D4 D3 D2 D1 D0 NEW_DATA 11 12 AVS PEN_OFF OSCIN YX+ V REF AIN0 AIN1 AVD Y+ X23 22 INT ST
44 1 V BAT X1 X2 AVG BHE COEN OUT_SELECT CONVERT PD_RESET PEN_SELECT ANSELIN

44-Pin MQFP (10 x 10 x 2mm) Package dimension information can be found at:
http://www.maxim-ic.com/TechSupport/DallasPackInfo.htm
ORDERING INFORMATION
DS1680FP-3 DS1680FP-5 3.3V Operation 5.0V Operation
DESCRIPTION
The DS1680 incorporates many functions necessary for low-power portable products, providing an RTC, NV RAM controller, microprocessor monitor, power- fail warning, 10-bit ADC, and a touch-screen controller in one chip. The RTC provides seconds, minutes, hours, day, date, month, and year information with leap-year compensation as well as an alarm interrupt. This interrupt works when the DS1680 is powered by the system power supply or when in battery-backup operation, so the alarm can be used to wake up a system that is powered down.
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110901
DS1680
Automatic backup and write protection of an external SRAM is provided through the VCCO and CEO pins. The backup energy source used to power the RTC is also used to retain RAM data in the absence of VCC through the VCCO pin. The chip-enable output to SRAM, CE0 , is controlled during power transients to prevent data corruption. The DS1680's microprocessor- monitor circuitry provides three basic functions. First, a precision temperature-compensated reference and comparator circuit monitors the status of VCC. When an out-oftolerance condition occurs, an internal power-fail signal is generated that forces RST to the active state. When VCC returns to an in- tolerance condition, the RST signal is kept in the active state for tRPU to allow the power supply and processor to stabilize. The DS1680 debounces a pus hbutton input and guarantees an active RST pulse width of tRST . The third function is a watchdog timer. The DS1680's internal timer forces the RST signal to the active state if the strobe input is not driven low prior to watchdog time-out. The DS1680 also provides a touch-screen controller along with a 10-bit successive approximation ADC. The ADC is monotonic (no missing codes) and has an internal analog filter to reduce high frequency noise.
DS1680 BLOCK DIAGRAM Figure 1
D0-D7 COEN PEN_SELECT OUT_SELECT BHE INT OUTPUT MUX RTC X2 X1
OSCIN
CLOCK OSC
CLOCK GEN SERIAL INTERFACE
SCLK CS I/O
AIN0 AIN1 INPUT MUX 10-BIT ADC
ST WATCHDOG RST NEW_DATA ANSELIN CONVERT PEN_OFF TOUCH DETECT CONVERT CONTROL VCC VBAT POWER SWITCH, WRITE PROTECT, NV CONTROL, AND POWER FAIL WARNING VCCO CEI CEO PFI X+ XY+ YPANEL DRIVE PFO
PD_RST
POWER CONTROL
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DS1680
SIGNAL DESCRIPTIONS
VCC , GND (Digital Supply and Digital Ground) - DC power to the RTC, watchdog, X and Y drivers, and power-switching circuitry is provided to the device on these pins. VBAT (Backup Power Supply) - Battery input for standard 3V lithium cell or other energy source. SCLK (Serial Clock Input) - SCLK is used to synchronize data movement on the serial interface. I/O (Data Input/Output) - The I/O pin is the bidirectional data pin for the 3-wire interface. CS (Chip Select) - The chip-select signal must be asserted high during a read or a write for communication over the 3-wire serial interface. VCCO (External SRAM Power Supply Output) - This pin is internally connected to VCC when VCC is within nominal limits. However, during power-fail VCCO is internally connected to the VBAT pin. Switchover occurs when VCC drops below VCCSW . INT (Interrupt Output) - The INT pin is an active-high output of the DS1680 that can be used as an interrupt input to a microprocessor. The INT output remains high as long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit is set. The INT pin operates when the DS1680 is powered by VCC or VBAT .
CEI (SRAM Chip-Enable Input) - CEI must be driven low to enable the external SRAM.
CEO (SRAM Chip-Enable Output) - Chip-enable output for SRAM.
PFI (Power-Fail Input) - Power- fail comparator input. When PFI is less than 1.25V, PFO goes low; otherwise PFO remains high. Connect PFI to GND or VCC when not used.
PFO (Power-Fail Output) - Power-fail output goes low and sinks current when PFI is less than 1.25V; otherwise PFO remains high. SI (Strobe Input) - The strobe input pin is used in conjunction with the watchdog timer. If the ST pin is not driven low within the watchdog time period, the RST pin is driven low. RST (Reset) - The RST pin functions as a microprocessor reset signal. This pin has an internal 47k pullup resistor.
X1, X2 - Connections for a standard 32.768kHz quartz crystal. For greatest accuracy, the DS1680 must be used with a crystal that has a specified load capacitance of 6pF. There is no need for external capacitors or resistors. Note: X1 and X2 are very high- impedance nodes. It is recommended that they and the crystal be guard-ringed with ground and that high- freque ncy signals be kept away from the crystal area. For more information about crystal selection and crystal layout considerations, please consult Application Note 58, "Crystal Considerations with Dallas Real-Time Clocks." The DS1680 will not function without a crystal.
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DS1680
AVD, AVS (ADC Supply and Ground) - Power supply and ground for the ADC. AIN0, AIN1 (Analog Inputs) - These pins are the analog inputs for the ADC. VREF (Voltage Reference) - Reference voltage for the ADC. X+, X- (Resistive Tablet X Plane Driver) - Connect to X-terminal of resistive tablet. Y+, Y- (Resistive Tablet Y Plane Driver) - Connect to Y-terminal of resistive tablet. CONVERT - Assert to logic 1 to request sample from AIN0 or AIN1. Use with ANSELIN input. ANSELIN (Analog Select Input) - Assert to logic 0 to select AIN0. Assert to logic 1 to select AIN1. Use with CONVERT input. BHE (Bus High Enable Input) - Drive to logic 1 to select high byte (data bits 2-9). Drive to logic 0 to select low byte (data bits 0-1). The lower 6 bits will all be zeros when asserted low. PEN_SELECT (Pen Select Input) - Assert to logic 1 to select X- or Y- data output. Assert to logic 0 to select AIN0 or AIN1 data output. Use with OUT_SELECT input. OUT_SELECT (Output Select Input) - Assert to logic 0 to select AIN0 or X- data. Assert to logic 1 to select AIN1 or Y- data. Use with PEN_SELECT input.
COEN (Chip Output Enable) - The COEN pin must be asserted low to enable the ADC data to be read on D0-D7.
D0-D7 (Data Bus) - Data output from ADC. AVG (Data Average Select Pin) - Logic 1 selects data average mode; logic 0 selects raw data mode.
NEW_DATA (New Data Indicator) - A logic 0 pulse indicates that new data packet is available on D0-D7.
OSCIN (Oscillator Input) - Input for the ADC clock. PEN_OFF (Pen Detection Output) - Indicates pen not detected. Logic 1 if pen is not detected. PD_RESET (Power Down/Reset Input) - Assert logic 1 for 10ns to reset. Hold at logic 1 for powerdown mode of the analog circuitry.
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DS1680
3-WIRE SERIAL INTERFACE
Communication with the RTC and watchdog is accomplished through a simple 3-wire interface consisting of the chip select (CS), serial clock (SCLK), and input/output (I/O) pins. All data transfers are initiated by driving the CS input high. The CS input serves two functions. First, CS turns on the control logic, which allows access to the shift register for the address/command sequence. Second, the CS signal provides a method of terminating either single byte or multip le byte (burst) data transfer. A clock cycle is a sequence of a rising edge followed by a falling edge. For data input, data must be valid during the clock's rising edge and data bits are output on the clock's falling edge. If the CS input goes low, all data transfer terminates and the I/O pin goes to a high- impedance state. Address and data bytes are always shifted LSB first into the I/O pin. Any transaction requires the address/command byte to specify a read or write to a specific register followed by one or more bytes of data. The address byte is always the first byte entered after CS is driven high. The most significant bit ( RD /WR) of this byte determines if a read or write will take place. If this bit is 0, one or more read cycles will occur. If this bit is 1, one or more write cycles will occur. Data transfers can occur one byte at a time or in multiple-byte burst mode. After CS is driven high an address is written to the DS1680. After the address, one or more data bytes can be read or written. For a single byte transfer one byte is read or written and then CS is driven low. Multiple bytes can be read or written to the DS1680 after the address has been written. Each read or write cycle causes the register address to automatically increment. Incrementing continues until the device is disabled. After accessing register 0Dh, the address wraps to 00h. Data transfer for single-byte transfer and multiple-byte burst transfer is illustrated in Figures 2 and 3.
SINGLE-BYTE DATA TRANSFER Figure 2
MULTIPLE-BYTE BURST TRANSFER Figure 3
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DS1680
ADDRESS/COMMAND BYTE
Figure 4 shows the command byte for the DS1680. Each data transfer is initiated by a command byte. Bits 0-6 specify the address of the registers to be accessed. The MSB (bit 7) is the read/write bit. This bit specifies whether the accessed byte will be read or written. A read operation is selected if bit 7 is a zero and a write operation is selected if bit 7 is a one. The address map for the DS1680 is shown in Figure 5.
ADDRESS/COMMAND BYTE Figure 4
7
RD WR
6 A6
5 A5
4 A4
3 A3
2 A2
1 A1
0 A0
RTC/WATCHDOG ADDRESS MAP Figure 5
BIT7 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0 0 0 0 0 0 M M M M 10 SECONDS 10 MINUTES 12 10 HR 10 HR 24
A/P
BIT0 SECONDS MINUTES HOURS 0 DAY DATE MONTH YEAR SECONDS ALARM MINUTES ALARM HOUR ALARM
0 0 0 0 10 DATE 0 0 10 MO. 10 YEAR 10 SEC ALARM 10 MIN ALARM 12 10 HR 10 HR 24 A/P 0 0
0 0 DAY ALARM CONTROL REGISTER STATUS REGISTER WATCHDOG REGISTER
RESERVED
7F
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DS1680
CLOCK, CALENDAR, AND ALARM
The time and calendar information is accessed by reading/writing the appropriate register bytes. Note that some bits are set to zero. These bits will always read zero regardless of how they are written. Also note that registers 0Eh to 7Fh are reserved. These registers will always read zero regardless of how they are written. The contents of the time, calendar, and alarm registers are in the binary-coded decimal (BCD) format. The DS1680 can run in either 12- hour or 24- hour mode. Bit 6 of the hours register is defined as the 12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic one being PM. In the 24- hour mode, bit 5 is the second 10- hour bit (20-23 hours). The DS1680 also contains a time-of-day alarm. The alarm registers are located in registers 07h to 0Ah. Bit 7 of each of the alarm registers are mask bits (Table 1). When all of the mask bits are logic 0, an alarm will occur once per week when the values stored in time-keeping registers 00h to 03h match the values stored in the time-of-day alarm registers. An alarm will be generated every day when mask bit of the day alarm register is set to one. An alarm will be generated every hour when the day and hour alarm mask bits are set to one. Similarly, an alarm will be generated every minute when the day, hour, and minute alarm mask bits are set to one. When day, hour, minute, and second alarm mask bits are set to one, an alarm will occur every second.
TIME-OF-DAY ALARM BITS Table 1
ALARM REGISTER MASK BITS (BIT 7) Seconds Minutes Hours Day 1 1 1 1 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0 Alarm once per second. Alarm when seconds match. Alarm when minutes and seconds match. Alarm when hours, minutes and seconds match. Alarm when day, hours, minutes and seconds match.
SPECIAL PURPOSE REGISTERS
The DS1680 has two additional registers (control register and status register) that control the RTC and interrupts.
CONTROL REGISTER - 0Bh
BIT 7
EOSC
BIT 6 WP
BIT 5 SP1
BIT 4 SP0
BIT 3 0
BIT 2 0
BIT 1 0
BIT 0 AIE
EOSC (Enable Oscillator) - This bit, when set to logic 0, will start the oscillator. When this bit is set to a logic 1, the oscillator is stopped and the DS1680 is placed into a low-power standby mode (IBAT ) when in battery-backup mode. When the DS1680 is powered by VCC, the oscillator is always on regardless of the status of the EOSC bit; however, the RTC is incremented only when EOSC is a logic 0.
SP0 and SP1 (Speed Select) - These bits select the on time of the X- and Y- measurement duty cycle. The programmable duty cycle section has more detail. WP (Write Protect) - Before any write operation to the RTC or any other registers, this bit must be logic 0. When high, the write-protect bit prevents a write operation to any register.
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DS1680
AIE (Alarm Interrupt Enable) - When set to a logic 1, this bit permits the interrupt request flag (IRQF) bit in the status register to assert INT. When the AIE bit is set to logic 0, the IRQF bit does not initiate the INT signal.
STATUS REGISTER - 0Ch
BIT 7 0 BIT 6 LOBAT BIT 5 0 BIT 4 0 BIT 3 0 BIT 2 0 BIT 1 0 BIT 0 IRQF
LOBAT (Low Battery Flag) - This bit reflects the status of the backup power source connected to the VBAT pin. When V is greater than 2.5V, LOBAT is set to a logic 0. When V is less than 2.3V, BAT BAT LOBAT is set to a logic 1. IRQF (Interrupt Request Flag) - A logic 1 in the interrupt request flag bit indicates that the current time has matched the time of day alarm registers. If the AIE bit is also a logic 1, the INT pin will go high. IRQF is cleared by reading or writing to any of the alarm registers.
POWER-UP/POWER-DOWN CONSIDERATIONS
When VCC is applied to the DS1680 and reaches a level greater than V CCTP (trip point), the device becomes fully accessible after tRPU (250ms typical). Before tRPU elapses, some inputs are disabled. When VCC drops below VCCSW , the device is switched over to the VBAT supply. During power- up, when VCC returns to an in-tolerance condition, the RST pin is kept in the active state for 250ms (typical) to allow the power supply and microprocessor to stabilize.
NONVOLATILE SRAM CONTROLLER
The DS1680 provides automatic backup and write protection for an external SRAM. This function is provided by gating the chip-enable signal and by providing a constant power supply through the VCCO pin. The DS1680 nonvolatizes the external SRAM by write-protecting the SRAM and by providing a backup power supply in the absence of VCC. When VCC falls below VCCTP , access to the external SRAM is prohibited by forcing CE0 high regardless of the level of CEI . Upon power-up, access is prohibited until the end of t RPU.
POWER-FAIL COMPARATOR
The PFI input is connected to an internal reference. If PFI is less than 1.25V, PFO goes low. The powerfail comparator can be used as an undervoltage detector to signal an impending power supply failure. PFO can be used as a P interrupt input to prepare for power-down. For battery conservation, the comparator is turned off and PFO is held low when in battery-backup mode.
ADDING HYSTERESIS TO THE POWER-FAIL COMPARATOR
Hysteresis adds a noise margin to the power-fail comparator and prevents PFO from oscillating when VIN is near the power- fail comparator trip point. Figure 6 shows how to add hysteresis to the power- fail comparator. Select the ratio of R1 and R2 such that PFI sees 1.25V when VIN falls to the desired trip point (VTRIP). Resistors R2 and R3 adds hysteresis. R3 will typically be an order of magnitude greater than R1 or R2. R3 should be chosen so it does not load down the PFO pin. Capacitor C1 adds noise filtering and has a value of typically 1.0F (See Figure 6 for a schematic diagram and equations.)
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DS1680
POWER-FAIL COMPARATOR Figure 6
+5V
VCC
R1
VIN
C1 R2 R3
PFI
DS1680
PFO GND
to P
R1 + R2 VTRIP = 1.25 R2
R2||R3 VH= 1.25 / R1 + R2||R3
VI - 1.25 R1
5 - 1.25 + R3 =
1.25 R2
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DS1680
MICROPROCESSOR MONITOR
The DS1680 monitors three vital conditions for a microprocessor: power supply, software execution, and external override. First, a precision temperature-compensated reference and comparator circuit monitors the status of VCC. When an out-of-tolerance condition occurs, an internal power-fail signal is generated that forces the RST pin to the active state, thus warning a processor-based system of impending power failure. When V CC returns to an in- tolerance condition upon power-up, the reset signal is kept in the active state for tRST to allow the power supply and microprocessor to stabilize. Note, however, that if the EOSC bit is set to a logic 1 (to disable the oscillator during battery-backup mode), the RST signal will be kept in an active state for t RST plus the start-up time of the oscillator. The second monitoring function is pushbutton reset control. The DS1680 provides for a pushbutton switch to be connected to the RST output pin. When the DS1680 is not in a reset cycle, it continuously monitors the RST signal for a low-going edge. If an edge is detected, the DS1680 will debounce the switch by pulling the RST line low. After the internal timer has expired, the DS1680 will continue to monitor the RST line. If the line is still low, the DS1680 will continue to monitor the line looking for a rising edge. Upon detecting release, the DS1680 will force the RST line low and hold it low for tRST . The third microprocessor monitoring function provided by the DS1680 is a watchdog timer. The watchdog timer function forces RST to the active state when the ST input is not stimulated within the predetermined time period. The time period is set by the time delay (TD) bits in the watchdog register. The time delay can be set to 250ms, 500ms, or 1000ms. If TD0 and TD1 are both set to zero, the watchdog timer is disabled. When enabled, the watchdog timer starts timing out from the set time period as soon as RST is inactive. The default setting is for the watchdog timer to be enabled with 1000ms time delay. If a high-to- low transition occurs on the ST input pin prior to time-out, the watchdog timer is reset and begins to time-out again. If the watchdog timer is allowed to time-out, the RST signal is driven to the active state for tRST . The ST input can be derived from microprocessor address signals, data signals, and/or control signals. To guarantee that the watchdog timer does not time-out, a high-to- low transition must occur at or less than the minimum period.
WATCHDOG REGISTER - 0Dh
BIT 7 0 BIT 6 0 BIT 5 0 BIT 4 0 BIT 3 0 BIT 2 0 BIT 1 TD1 BIT 0 TD0
WATCHDOG TIME-OUT BITS Table 2
TD1 0 0 1 1 TD0 0 1 0 1 WATCHDOG TIME-OUT Watchdog Disabled 250ms 500ms 1000ms
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DS1680
RESISTIVE TOUCH SCREEN (4-WIRE)
Resistive touch screens consist of two resistive plates that are separated by a small gap. Each plate has an electrode at each end; when the screen is touched the pressure forces the two plates to come in contact at the exact position of the touch. To get the x-coordinate position, the DS1680 will drive the X -plane resistive film (via X+ and X-) and sense the voltage picked up by the Y-plane resistive film (via Y+ and Y-). Next, to get the y-coordinate position, the DS1680 will drive the Y- plane resistive film and sense the voltage picked up by the X-plane resistive film.
ANALOG-TO-DIGITAL CONVERTER (ADC)
The DS1680 provides a 10-bit ADC. Two multiplexed analog inputs are provided through the AIN0 and AIN1 pins along with two other inputs on the X- and Y- pins. The ADC is monotonic (no missing codes) and uses a successive approximation technique to convert the analog signal into a digital code. An analog-to-digital conversion is the process of assigning a digital code to an analog input voltage. This code represents the input value as a fraction of the full-scale voltage (FSV) range. The FSV range is then divided by the ADC into 1024 codes (10 bits), and is bound by an upper limit equal to the reference voltage and the lower limit, which is ground. On-chip circuitry detects if the pen is in contact with the digitizer tablet. The pen-detection status is indicated on pin (PEN_OFF) and can be used by the system for signaling end-of-stroke for handwriting recognition software purposes. If no pen is detected, PEN_OFF will be pulled to logic 1 and no coordinate data will be made available. PEN_OFF at logic 0 indicates that a pen is detected on the digitizer tablet and its coordinate position will be made available on D0-D7. The NEW_DATA pin pulses low to indicate when a new coordinate data pair is available. When the AVG pin is set to logic 0, the data at pins D0-D7 will indicate the most recent sample of the ADC. Setting the AVG pin to logic 1 invokes the data averaging mode. In this mode, the data output on D0-D7 will indicate the rolling average of the four most recent samples of the ADC. The DS1680 continuously monitors the CONVERT and ANSELIN signals; on the internal clock's rising edge (state cycle), the corresponding AIN0 or AIN1 conversion is requested. The conversion request must be completed before T0 (Figure 7c) in order for AIN0 and/or AIN1 to be sampled and converted in the present conversion cycle; otherwise AIN0 and/or AIN1 will be sampled and converted in the next conversion cycle. The logic level of the ANSELIN input will determine whether a sample is taken from the AIN0 or AIN1 input. Table 3 lists the specific analog input that is selected by this signal. Figure 8 shows the required timing associated with CONVERT and ANSELIN. If the state of ANSELIN changes while CONVERT is at logic 1 and you meet the timing requirements of figure 8, both AIN0 and AIN1 conversions are requested. If the ANSELIN does not change states while CONVERT is at logic 1, only AIN0 or AIN1 conversion is requested. If a pen is detected during a conversion request, then X and Y will be sampled and converted prior to the AIN0 and/or AIN1 conversion. The AIN0 and AIN1 conversion result is output on the D0-D7 as defined in the Parallel Interface section.
ANALOG INPUT SELECTION Table 3
ANSELIN 0 1 ANALOG INPUT AINO AIN1
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DS1680
PROGRAMMABLE DUTY CYCLE
The current required to take an X or Y measurement is V AVD / RD. In the case of RD = 250O and VAVD = 5V, the current required is 20mA. The average current is the current during the measurement, multiplied by the ratio of the time the drivers are on, to the power of total sample time. In order to minimize the average current, the on-time should be limited to the minimum time required for the tablet RC delay. Experimental data suggests that a typical RC time constant is between 4s and 5s for a resistive touch screen. In order to achieve 10-bit resolution, the settling time must be eight time constants. This creates a requirement of a minimum of 80s on-time total, 40s for each X and Y measurement. To provide both low power and high sample rate, the on-time for the X- and Y- measurement duty cycle is programmable. Bits 4 and 5 (SP0 and SP1) of the control register (0Bh) select the on-time of four different frequency ranges. The frequencies given are the maximum frequency for that timing range, which will not violate the 40s-per- measurement requirement. SP1 SP0 FREQUENCY RANGE (MHz) 2.0 2.8 4.0 5.0 AVERAGE CURRENT (A) 870 1.217m 1.739m 2.261m SAMPLES/SEC 543 760 1086 1359 NO. OF CYCLES 5 7 10 13
0* 0* 0 1 1 0 1 1 *This is the default setting
Average current is the current required for the measurement, averaged out over the entire sample. This average current is only related to the measurement phase when the drivers are on. The average current will be drawn from the VCC supply. There is also current associated with the pen-detection phase, the ADC, and the control logic. The number of cycles indicated is the number of on-time state cycles. One state cycle is 16 main clock cycles. If the frequency range is 2.0MHz, the state frequency is 2MHz/16 = 125kHz. There are 230 state cycles in one complete sample. The number of cycles can be used to calculate the settling time and the sample rate. Example 1: Frequency Range : 2.0MHz Input Clock Frequency : 1.8432MHz tsettle = (1 / 1.8432e6) x 16 x 5 = 43.4s Iavg = (10 / 230) x 20mA = 870A Sample Rate = 1.8432e6 / (16 x 230) = 501 samples/sec Example 2: Frequency Range : 2.8MHz Input Clock Frequency : 1.8432MHz tsettle = (1 / 1.8432e6) x 16 x 7 = 60.8s Iavg = (14 / 230) / x 20mA = 1.217mA Sample Rate = 1.8432e6 / (16 x 230) = 501 samples/sec
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DS1680
CONVERSION TIMING Figure 7a
Pen Down
X-Y Measure PD X Y PD A0 - A1 Measure A0 A1 PD X Y PD A0 A1 PD X Y PD A0 A1 PD X Y PD A0 A1 PD X Y PD
PEN_OFF
AVG = 0 (Disabled)
NEW_DATA
AVG = 1 (Enabled)
NEW_DATA
X to Y MEASUREMENT Figure 7b
115 state cycles 30 PD 10-18 13-5
11 1001 00 X-drivers on
28-36
13-5
111001 00 Y-drivers on
21
30 PD 1 State Cycle = 16 Main Clock Cycles
AIN0 to AIN1 MEASUREMENT Figure 7c
115 state cycles 30 PD 18 6 A0 35 6 A1 20 30 PD 1 State Cycle = 16 Main Clock Cycles T0
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DS1680
CONVERT AND ANSELIN TIMING Figure 8
must be at least 2 state cycles
CONVERT
AIN0 conversion requested
ANSELIN = 0
must be at least 4 state cycles
CONVERT
both AIN0 and AIN1 conversion requested
ANSELIN
must be at least 2 state cycles
must be at least 2 state cycles
must be at least 2 state cycles
CONVERT
AIN1 conversion requested
ANSELIN = 1
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DS1680
PARALLEL INTERFACE
The ADC output is available on the data bus at pins D0-D7. A logic 0 on COEN will enable data onto the data bus so that the DS1680 can be used in parallel with other devices. PEN_SELECT and OUT_SELECT are used to decode which analog output (X-, Y-, AIN0, or AIN1) is output on the data bus when COEN is asserted low. Since the device offers 10-bit resolution, the BHE pin is used to decode the 10 bits of data on the data bus. A logic 1 on BHE will enable data bits B2-B9. A logic 0 will enable data bits B0-B1 along with the six LSBs = 0. The status pin ( NEW_DATA ) pulses low to indicate that new coordinate or conversion is available. The output can be read while NEW_DATA is low or after it has gone high. Output selection and parallel data format is shown below.
OUTPUT SELECTION Table 4
PEN_SELECT 0 0 1 1 OUT_SELECT 0 1 0 1 ANALOG OUTPUT AIN0 AIN1 XY-
PARALLEL DATA FORMAT
High Byte Low Byte BHE = 1 BHE = 0 MSB B9 B1 B8 B0 B7 0 B6 0 B5 0 B4 0 B3 0 LSB B2 0
POWER MANAGEMENT (ADC AND PEN-INPUT PROCESSOR)
The DS1680 analog circuitry can be placed into a low-power mode by asserting and holding the PD_RESET pin at logic 1. Normal operation will resume when PD_RESET is returned to logic 0. To further conserve power, the pen-detection circuitry will automatically switch the analog circuitry to power-down mode whenever there is no pen input detected for more than three seconds. Normal operation will automatically resume when any one of the following three events occur: pen down is detected, the CONVERT signal is activated, or chip is reset (PD_RESET pulled to logic 1 and then returned to logic 0).
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DS1680
ABSOLUTE MAXIMUM RATINGS*
Voltage Range on Any Pin Relative to Ground Operating Temperature Range Storage Temperature Range Soldering Temperature Range -0.3V to +7.0V 0C to +70C -55C to +125C See J-STD-020A Specification
*This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER Digital Power Supply Voltage 3.3V Operation Digital Power Supply Voltage 5V Operation Input Logic 1 Input Logic 0 Battery Voltage SYMBOL VCC, VAVD, VREF VCC, VAVD, VREF VIH VIL VBAT MIN 2.97 4.5 2.0 -0.3 2.5 TYP 3.3 5.0 MAX 3.63 5.5
VCC + 0.3
(0C to +70C)
UNITS V V V V V NOTES
+0.8 3.7
DC ELECTRICAL CHARACTERISTICS
PARAMETER Input Leakage CS Leakage Logic 1 Output (IOUT = -0.4mA) Logic 0 Output (IOUT = 1.5mA) Active Supply Current (No Pen Detect) Active Supply Current (Pen Detected) Standby Current Oscillator Current Battery Current (Oscillator Off) Internal RST Pullup Resistor VCC Trip Point VCC Switchover Pushbutton Detect Pushbutton Release Output Voltage VCCO Output Current (Source = VCC ) VCCO Output Current (Source = VBAT) PFI Input Threshold PFI Input Leakage
PFO PFO
(0C to +70C; V CC = 5.0V 10%)
MIN -1 2.4 200 175 300 25 4.15 0.8 0.3
VCC - 0.3
SYMBOL ILI ILO VOH VOL ICCA ICCPD ICCS IOSC IBAT RP VCCTP VCCSW PBDV PBRD VCCO ICCO1 ICCO2 VPFI IPFI VOH VOL
TYP
MAX +1 260 0.4 500 5 300 500 100 87 4.50 2.78 2.0 0.8 150 150 1.35 25
47 4.33 2.67
1.15 -25
VCC - 1.5
1.25
UNITS A A V V A mA A nA nA k V V V V V mA A V nA V
NOTES 7 1 2 3 19 4 17 18
12, 20
11 13 14
Output Voltage, IOH = -0.4mA Output Voltage, IOL = 1.5mA
0.4
V
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DS1680
DC ELECTRICAL CHARACTERISTICS
PARAMETER Input Leakage CS Leakage Logic 1 Output (IOUT = -0.4mA) Logic 0 Output (IOUT = 1.5mA) Active Supply Current (No Pen Detect) Active Supply Current (Pen Detected) Standby Current Oscillator Current Battery Current (Oscillator Off) Internal RST Pullup Resistor VCC Trip Point VCC Switchover Pushbutton Detect Pushbutton Release Output Voltage VCCO Output Current (Source = VCC ) VCCO Output Current (Source = VBAT) PFI Input Threshold PFI Input Leakage
PFO PFO
(0C to +70C; V CC = 3.3V 10%)
TYP MAX +1 170 0.4 300 3 200 500 100 87 2.97 2.78 2.0 0.8 80 100 1.35 25 0.4 UNITS A A V V A mA A nA nA k V V V V V mA A V nA V V NOTES 7 1 2 3 19 4 17 18
Output Voltage, IOH = -0.4mA Output Voltage, IOL =1.5mA
SYMBOL MIN ILI -1 ILO VOH 2.4 VOL ICCA ICCPD ICCS IOSC IBAT RP 25 VCCTP 2.75 VCCSW PBDV 0.8 PBRD VCCO VCC-0.3 ICCO1 ICCO2 VPFI 1.15 IPFI -25 VOH VCC-1.5 VOL
115 110 300 47 2.86 2.67 0.3
12, 20
11 13 14
1.25
CAPACITANCE
PARAMETER Input Capacitance I/O Capacitance Crystal Capacitance SYMBOL CI CI/O CX MIN TYP 10 15 6 MAX
(TA = +25C)
UNITS pF pF pF NOTES
3-WIRE INTERFACE CHARACTERISTICS
PARAMETER Data to Clock Setup CLK to Data Hold CLK to Data Delay CLK to Low Time CLK to High Time CLK Frequency CLK Rise and Fall CS to CLK Setup CLK to CS Hold CS Inactive Time CS to I/O High- Z SYMBOL tDC tCDH tCDD tCL tCH tCLK tR, tF tCC tCCH tCWH tCDZ MIN 50 70 250 250
(0C to +70C; V CC = 5.0V 10%)
TYP MAX UNITS ns ns ns ns ns MHz ns s ns s ns NOTES 8 8 8, 9, 10 8 8 8 8 8 8 8
200
2.0 500 1 250 1 70
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DS1680
3-WIRE INTERFACE CHARACTERISTICS
PARAMETER Data to Clock Setup CLK to Data Hold CLK to Data Delay CLK to Low Time CLK to High Time CLK Frequency CLK Rise and Fall CS to CLK Setup CLK to CS Hold CS Inactive Time CS to I/O High- Z SYMBOL tDC tCDH tCDD tCL tCH tCLK tR, tF tCC tCCH tCWH tCDZ MIN 150 210 750 750
(0C to +70C; V CC = 3.3V 10%)
TYP MAX UNITS ns ns ns ns ns MHz ns s ns s ns NOTES 8 8 8, 9, 10 8 8 8 8 8 8 8
600
0.667 1500 3 750 3 210
ADC CHARACTERISTICS
PARAMETER Resistance of Digitizer Film Resistance of On-Chip Driver Parasitic Capacitance Between Xand Y-Plates of Digitizer Ladder Resistance ADC Active Current ADC Standby Current Reference Current Input Leakage (AIN0, AIN1) Analog Input Capacitance Resolution Differential Nonlinearity Integral Nonlinearity Offset Error Gain Error ADC Clock Frequency Multiplexer Selector Path Propagation Delay COEN Falling Edge to Data Bus Driven COEN Rising Edge to Data Bus High-Z EDL EIL EOS EG FOSCIN tMUX tOEA tOEZ SYMBOL RD RDRIVER CXY RREF IAVDA IAVDS IREF ILI CIN
(0C to +70C; VCC, VAVD = 5.0V 10%)
MIN 250 TYP 600 12 5 8 25 450 120 200 10 10 10 0.5 0.5 1.0 0.25 1.0 1.0 1.5 1.0 5.0 60 40 40 15 MAX 1000 25 10 60 650 200 650 UNITS nF k A A A nA pF Bits LSB LSB LSB % MHz ns ns ns 5 6 NOTES
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DS1680
ADC CHARACTERISTICS
PARAMETER Resistance of Digitizer Film Resistance of On-Chip Driver Parasitic Capacitance Between Xand Y-Plates of Digitizer Ladder Resistance ADC Active Current ADC Standby Current Reference Current Input Leakage (AIN0, AIN1) Analog Input Capacitance Resolution Differential Nonlinearity Integral Nonlinearity Offset Error Gain Error ADC Clock Frequency Multiplexer Selector Path Propagation Delay
COEN Falling Edge to Data Bus
(0C to +70C; VCC, VAVD = 3.3V 10%)
SYMBOL RD RDRIVER CXY RREF IAVDA IAVDS IREF ILI CIN 8 MIN 250 TYP 600 15 5 25 320 50 150 10 10 10 EDL EIL EOS EG FOSCIN tMUX tOEA tOEZ 0.5 0.5 1.0 0.25 1.0 1.0 1.5 1.0 2.5 120 80 80 15 MAX 1000 30 10 60 450 150 550 UNITS nF k A A A nA pF Bits LSB LSB LSB % MHz ns ns ns 5 6 NOTES
Driven
COEN Rising Edge to Data Bus
High-Z
POWER-FAIL AND RESET CHARACTERISTICS (0C to +70C; VCC = 5.0V 10%)
PARAMETER PFI Low to PFO Low PFI High to PFO High VCC Detect to RST (VCC Falling) VCC Detect to RST (VCC Rising) Reset Active Time Pushbutton Debounce ST Pulse Width Chip-Enable Propagation Delay to External SRAM VCCTP(MAX) to VCCSW(MIN) Fall Time SYMBOL tPFD tPFU tRPD tRPU tRST PBDB tST tCED tFB
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MIN
TYP
MAX 100 100 100
UNITS ns ns ns ms ms ms ns ns s
NOTES
250 250 250 20 8 200 15
15,16 15 15
20
DS1680
POWER-FAIL AND RESET CHARACTERISTICS (0C to +70C; V CC = 3.3V 10%)
PARAMETER PFI Low to PFO Low PFI High to PFO High VCC Detect to RST (VCC Falling) VCC Detect to RST (VCC Rising) Reset Active Time Pushbutton Debounce ST Pulse Width Chip-Enable Propagation Delay to External SRAM VCCTP(MAX) to VCCSW(MIN) Fall Time SYMBOL tPFD tPFU tRPD tRPU tRST PBDB tST tCED tFB MIN TYP MAX 200 200 200 250 250 250 40 8 50 15 UNITS ns ns ns ms ms ms ns ns s NOTES
15, 16 15 15
20
PARALLEL INTERFACE OUTPUT TIMING Figure 9
COEN tOEA
tOEZ
PEN_SELECT tMUX
OUT_SELECT tMUX tMUX
BHE tMUX t MUX tMUX tMUX
D0 - D7
X, HIGH
X, LOW
Y, HIGH
Y, LOW
AIN0, HIGH
AIN0, LOW
AIN1, LOW
AIN1, LOW
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DS1680
3-WIRE TIMING DIAGRAM: READ DATA Figure 10
3-WIRE TIMING DIAGRAM: WRITE DATA Figure 11
PUSHBUTTON RESET Figure 12
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DS1680
VCC POWER-UP Figure 13
VCC POWER-DOWN Figure 14
POWER-FAIL WARNING Figure 15
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DS1680
NOTES:
1. Logic 1 voltages are specified at VCC = 3.3V or 5.0V, VOH = VCC for capacitive loads. Exclude RST pin. 2. Logic 0 voltages are specified at VCC = 3.3 or 5.0V, VOL = GND for capacitive loads. 3. ICCA is specified with outputs open, CS set to a logic 1, SCLK = 500kHz, oscillator enabled, ADC disabled, and no pen detected. 4. ICCS is specified with CS, VCCO open and I/O, SCLK at logic 0, ADC disabled, and no pen detected. 5. IAVDA is specified with ADC enabled. 6. IAVDS is specified with ADC disabled. 7. CS has a 40k pulldown resistor to ground. 8. Measured at VIH = 2.0V or VIL = 0.8V and 10ns maximum rise and fall time. 9. Measured at VOH = 2.4V or VOL = 0.4V. 10. Load capacitance = 25pF. 11. ICCO = 100 mA, VCC > VCCTP . 12. VCCO switchover from VCC to VBAT occurs when VCC drops below the lower of VCCSW and VBAT . 13. Current from VCC input pin to VCCO output pin. 14. Current from VBAT input pin to VCCO output pin. 15. Timebase is generated by the crystal oscillator. Accuracy of this time period is based on the 32kHz crystal that is used. A typical crystal with a specified load capacitance of 6pF will provide accuracy within 100ppm over the 0C to +70C temperature range. For greater accuracy, see the DS32kHz data sheet. 16. If the EOSC bit in the control register is set to a logic 1, tRPU is equal to 250ms plus the start-up time of the crystal oscillator. 17. VCC = 0V, VAVD = 0V, VBAT = 3.7V. and oscillator enabled. Measured without RAM connected. 18. VCC = 0V, VAVD = 0V, VBAT = 3.7V, and oscillator disabled. Measured without RAM connected. 19. ICCPD is specified with outputs open, CS set to a logic 1, SCLK = 500kHz, oscillator enabled, ADC enabled, and pen detected. 20. Under certain slew rate conditions, VSW can be as low as 1.8V.
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